1. Field of the Invention
Example embodiments of the present invention generally relate to a semiconductor memory device. More particularly, example embodiment of the present invention relate to a semiconductor memory device in which memory cells are tested using several different test data patterns and method thereof.
2. Description of the Related Art
As the capacity of a semiconductor memory device has increased, so has the time required to test the semiconductor memory device. Accordingly, in order to reduce the test time, several semiconductor memory devices may be tested at the same time using a single test apparatus.
The number of input/output (I/O) pins capable of being tested by a single test apparatus is fixed, therefore, to test additional semiconductor memory devices at the same time, it may be necessary to reduce the number of I/O pins allocated to a memory device.
To test a semiconductor memory device using fewer number of I/O pins, the semiconductor memory device may be adapted to operate in a test mode in addition to a normal mode. In the test mode, the semiconductor memory device may process and output several internal parallel data through the I/O pins, and may expand and write data received through the I/O pins as parallel data.
However, when data received through the fewer number of I/O pins are expanded and several internal parallel data are generated, data patterns capable of being written in memory cells may not be varied.
FIG. 1 illustrates a conventional semiconductor memory device 100 capable of expanding input data and generating parallel data.
Referring to FIG. 1, the memory device 100 may include a plurality of transmission gates TG11 to TG116 and TG21 to TG216. In a normal mode, the transmission gates TG11 to TG116 in response to a normal mode signal MODE_N may transfer received data DIN1 to DIN16 to corresponding memory cells (not shown). The normal mode signal MODE_N may be applied to NMOS transistors of the transmission gates TG11 to TG116, and an inverted normal signal MODE_N, inverted by an inverter 11, may be applied to PMOS transistors of the transmission gates TG11 to TG116.
During a test mode, the transmission gates TG21 to TG216 may apply received data DIN1, DIN5, DIN9, and DIN13 in response to a test mode signal MODE_T to corresponding memory cells (not shown).
The test mode signal MODE_T may be applied to NMOS transistors of the transmission gates TG21 to TG216, and an inverted test mode signal MODE_T, inverted by an inverter 12, may be applied to PMOS transistors of the transmission gates TG21 to TG216.
As described above, in order for a single test apparatus to test several semiconductor memory devices at one time, the number of I/O pins allocated to a memory device must be reduced. The memory device 100 illustrated in FIG. 1 has an “×16” organization in which 16 data bits may be input/output at the same time, and the number of I/O pins used during the testing may be four.
The memory device 100 takes the four data DIN1, DIN5, DIN9, and DIN13 in a test mode and generates (expands) 16 data DATA1 to DATA16 to be applied to the memory cells. The data DATA1 to DATA16 may be respectively written to the corresponding memory cells.
Since the memory device 100 uses only four input data DIN1, DIN5, DIN9, and DIN13 during a test mode, the same value as the input data DIN1 may be written to the memory cells to which data DATA1, DATA2, DATA3, and DATA4 may be applied.
Likewise, the same value as the input data DIN5 may be written to the memory cells to which data DATA5, DATA6, DATA7, and DATA8 may be applied. This process also applies to DIN9 and DIN13.
In general, in order to detect a defective semiconductor memory device, several different test data patterns may be required. However, as described above, it may not possible for the semiconductor memory test circuit 100 with the “×16” organization to have a value data DATA1 that is different than a value of data DATA2. In the memory device 100, the number of test data patterns capable of being used in a test mode may be limited.
FIG. 2 illustrates a conventional test data pattern generator 200.
As described above with respect to the memory device 100 of FIG. 1, the number of test data patterns may be limited.
In order to solve the problem of the limited test data patterns available during a test mode, an address key method of combining input data DIN1 to DINn with dummy addresses ADD1 to ADDm to generate test data patterns P_DATA1 to P_DATAn has been introduced in the conventional art.
However, because the number of available test data patterns depends on the number of available addresses and input data, and the addresses must be varied according to the test data patterns, there may be compatibility issues of using the address key method with existing package test patterns.
FIG. 3 illustrates another conventional memory device 300 which may include a selector 310 to select either data DOI output from a memory cell (not shown) in a normal mode or select a test result signal TRS in a test mode, in response to a mode control signal MODE. The memory device 300 may further include an output buffer 320, and logic devices ENR1 to ENR16, and N1 to generate the test result signal TRS.
With reference to FIG. 3, a “merged DQ” method to reduce the number of I/O pins through which test results are output will be described. In the merged DQ method, test data values T_DATA1 to T_DATA16 stored in internal registers (not shown) may be respectively compared with data DOI1 to DOI16 read from memory cells, a pass/fail (P/F) may be determined from the comparison, and the determined result may be output through the output buffer 320. By using the merged DQ method, it may be possible to reduce the number of I/O pins and output buffers 320 during a test mode.
By respectively comparing test data values T_DATA1 to T_DATA16 stored in internal registers (not shown) with data DOI1 to DOI16 read from memory cells using logic devices ENR1 to ENR16, and N1, if at least one memory cell is defective, a test result signal TRS indicating the defect may be generated.
However, in the merged DQ method, problems still exist in that the method requires a predetermined command to change test data values T_DATA1 to T_DATA16 stored in internal registers (not shown) to be respectively compared with read data DOI1 to DOI16. In addition, it may be difficult to change the test data values T_DATA1 to T_DATA16. Accordingly, compatibility issues with test data patterns used with current test method still exists.